Custom
Silicon

Our experts understand your requirements and come up with the right architecture for your SoC. The analysis the various IPs that can become a part of your soc and suggest the most appropriate technology node in which the silicon can be built. They also explore the option of chipset architecture to see if that would suit the Power, Performance and Area(PPA) requirements of your Product.

The RTL design team at 7Rays Semiconductors is proficient in defining the architecture for SoC and micro-architecture for IPs or subsystems.
The team is capable of developing IPs from scratch and ensuring that they are IPXACT compliant. If it is a subsystem or SoC, the team is experienced with integrating the available IPs, including third-party IPs, and bringing up the SoC. Apart from this, the team has expertise in Lint, Clock Domain Crossing (CDC) & Low power static checks using industry-standard tools. As part of the deliverables, the team ensures that the design is synthesis & DFT-ready..

The Design verification team at 7Rays Semiconductors has expertise in defining the right strategy for verification based on the scope, i.e.
IP, Sub-system or SoC depending upon the reuse expected from legacy code, third party verification IPs etc. We are proficient with Coverage driven verification using UVM or other methodologies for IP level. At SoC level, if need be, bring up of C based flow along with reuse of IP level testbenches can be done. For verification, we follow metrics like code coverage, functional coverage & assertions where applicable. …The team has good experience with power aware simulations, developing tests for usecases/stress testing & AMS. For netlist simulations, the team is capable to bring up GLS testbench with zero/unit delay simulations or SDF simulations on targeted corners. We can further port the tests for test vector generation to improve test coverage on silicon.

Read more

Our in-house Design-For-Test(DFT) and Verification team has expertise in achieving high test coverage goals ensuring very high test quality and very low DPPM (Defective Parts Per Million) numbers for the SoCs we handle. Our excellence in devising custom test architecture solutions for our varied set of customers help us to stand out and deliver best in class SoCs with brilliant yield numbers and a thorough screen for catching any manufacturing defects which is very vital for our customers’ success.…We are capable of defining and developing Test RTL and IO MUX architecture scheme and taking the designs through various DFT stages like Boundary Scan(BSCAN), Memory Built-In Self Test(MBIST) and Scan phases by using Industry Standard EDA Tools for both hierarchical monolithic die and chiplet based multi-die design architectures. Our Test Team is not only self-sufficient in Development and Validation of Testmode constraints, but, also closely collaborates with the Backend Team for any scope for enhancements for better optimization of the designs.
Read more

Our expert team excels in Physical Design, Static Timing Analysis and Physical Verification. They are innovative and experienced in delivering advanced methodologies and tools to maximize performance, minimize power consumption and achieve optimal timing closure, resulting in first pass silicon-ready designs that meet your most demanding requirements. Our design implementation flow and methodology in Floor Planning, Placement and Clock Tree Synthesis enable us to time close even very high speed designs in a very predictable manner resulting in meeting
tight timelines of Tape-Outs.

We understand the anxiety when a wafer or chip arrives at the test facility after fabrication. Hence, we have a set of Silicon Bring-Up experts who get on to the mission of quickly bringing up silicon on arrival, debugging and fixing any set-up or ATE environment-related issues, and promptly reporting the Quality Check Points(QCP) that a freshly arrived sample achieves.

Silicon Debug is a very important part of the overall solutions that we provide. Our experts bring great value to the entire program when our customers hit a roadblock during their Silicon Bring-Up cycles. Our experts in the field of Silicon Debug are well versed with different Test Equipments and how test programs work. They can accurately isolate real design issues from issues introduced due to various factors in a test facility, test equipment, test programs, or test patterns. This adds great value to the overall execution of SoC deployment.